1. Field of the Invention
This invention relates to an operating system for a data transmission system in which data transmission between selected terminal units is controlled, and more particularly to an operating system adapted to facilitate system enlargement and maintenance in a data transmission system in which a plurality of data stations, each having connected thereto a plurality of terminal units via a common bus, are interconnected in a linear, circular or network form via transmission circuits.
2. Description of the Prior Art
In recent years, a data highway system has been used which makes use of time division multiplex transmission for the purpose of reducing fabrication and installation costs of transmission cables, and such system are now employed for plant control or the like. In such a data highway system, central control stations CPU1 and CPU2, each typically having an electronic computer or the like and a data station (hereinafter referred to as a port) P1 through P5, each having accommodated therein a plurality of terminal units, are interconnected in a loop, for example, as shown in FIG. 1, and data transmission is achieved between the central control stations and the terminal units or between the terminal units. Since the data transmission takes place via a pair of transmission lines in such a data highway system, there is a strong demand for easy system enlargement and maintenance, as compared with other conventional transmission system. To meet the demand, for instance, in the case of system enlargement, a port is installed in advance at the place of enlargement so as to enable the enlargement by an on-line operation, the terminal units to be newly added are connected to the port and their operation is checked for malfunction after the connection of a power source and so on, and then the port is connected to a data circuit that is already provided. In system maintenance, operation of all terminal units can be tested by an on-line operation at any one of the ports without the necessity of an operator going to each port set up at a remote location. Accordingly, in the prior art, system enlargement and maintenance is carried out relatively easily in terms of hardware, but in such sysem enlargement and maintenance, the system diagnosis is usually effected by a software manipulation, which introduces the possibility of applying a faulty command to a terminal unit in normal operation due to a program error or the like to exert a serious influence on the system, such as causing its breakdown. The cause of such a drawback is that there is not provided anywhere in conventional data transmission systems a device for inhibiting an erroneous access to a terminal unit during system diagnosis.
That is, the conventional port P1 used in the data transmission system of FIG. 1 comprises, as shown in FIG. 2, a processor coupling unit 1 having the function of controlling the interface between the port and the central control station CPU1, a device coupling unit 2 having a function of controlling the interface between the port and each terminal unit, a communication control unit 3 for transferring data to other ports via a line, a data bus 4a and a control bus 4b for the information transfer among the three units 1 through 3 and a bus controller 5 for controlling the buses. FIG. 2 indicates a processor coupling control circuit 11; a sending frame resister 12 for temporarily setting information from the central control station CPU1; a receiving frame register 13 for temporarily setting information to be sent to the central control station CPU1; input and output gate circuits G12a, G12b, G13a and G13b for the sending frame register 12 and the receiving frame register 13; a transfer request flip-flop 14; a decoder 15; a circuit 16 for controlling the interface between the port P1 and the central control station CPU1; a bus control circuit 51; an instruction word register 52 for temporarily setting an instruction word included in a transmission frame; a data word register 53 for temporarily setting a data word included in the transmission frame; an instruction word decoder 54; and input and output gate circuits 52a, 52b, 53a and 53b for the instruction word register 52 or the data word register 53.
Now, a description will be given of the operation of each unit, for example, in connection with the case of data from the central control station CPU1 being written in a terminal unit T11. At first, the data sent out from the central control station CPU1 and an instruction word composed of the destination of the data and like information are provided to the input gate circuit G12a and then set in the sending frame register 12 by a set signal SET from the interface control circuit 16. The sending and receiving frame registers 12 and 13 are respectively divided into two stages 12a, 12b and 13a and 13b, which are provided for transmitting one transmission frame in two transmission periods because the bus width of the data bus 4a is small. Where the bus width is large, the transmission frame can be sent out at one time and the receiving and sending frame registers may each be one-stage.
Immediately when detecting, by the signal SET, the setting of the data in the sending frame register 12, the processor coupling control circuit 11 sets the flip-flop 14 to derive therefrom an output "1" in preparation for a command from the bus control unit 5. The bus control circuit 51 of the bus control unit 5 controls the use of the bus by scanning addresses of respective processors connected to the data bus 4a. When the decoder 15 of the processor coupling unit 1 detects that the address scanning is directed to the processor coupling unit 1, the decoder 15 provides an output "1" to both the processor coupling control circuit 11 and the gate circuit G16. As a consequence, at this timing, the output from the gate circuit G16 becomes "1", which is applied as a transfer request signal RQ to the bus control circuit 51 via the control bus 4b. Upon receipt of the transfer request signal RQ from the processor coupling unit 1, the bus control circuit 51 stops the address scanning and allows the processor coupling unit 1 to exclusively use the data bus 4a and the control bus 4b and, at the same time, sends an instruction read signal R1 via the control bus 4b to the processor coupling unit 1. Receiving the instruction read signal R1, the processor coupling control circuit 11 applies a gate signal GR1 to the output gate circuit G12b, by which the instruction word in the transmission frame set in the sending frame register 12 is sent out first to the bus control unit 5 via the data bus 4a.
As the bus control circuit 51 also applies the instruction read signal R1 to the input gate circuit 52a of the instruction word register 52, the instruction word sent out from the processor coupling unit 1 is set in the instruction word register 52. Similarly, at the next timing, the bus control cuircuit 51 provides a data read signal R2, by which the data set in the sending frame register 12 is set in the data word register 53 of the bus control unit 5.
Then, the bus control circuit 51 decodes the instruction word in the instruction word register 52 by the decoder 54. When detecting that the content of the instruction word is an instruction for writing data in the terminal unit T11, the bus control circuit 51 provides an instruction word write signal W1 via the device coupling unit 2 to the terminal unit T11 and, at the same time, applies the instruction word write signal W1 to the output gate circuit 52b to open it, so that the instruction word set in the instruction word register 52 is written in the terminal unit T11 via the data bus 4a and the device coupling unit 2. In a likewise manner, the bus control circuit 51 generates a data word write signal W2, by which the data word set in the data word register 53 is written in the terminal unit T11.
The above is the operation of each unit in the case of writing the data from the central control station CPU1 in the terminal unit T11. Data transmission from the terminal unit T11 to the central processing unit CPU1 or from the central control staton CPU1 to a terminal unit T11 of another port via the communication control unit 3 is also performed in a similar manner.
As described above, in the conventional port, for example, if the transmission frame which is sent out from the central processing unit CPU1 to the terminal unit T11 for testing it is misaddressed to a terminal unit T1N, faulty data is written therein because there is not provided anywhere in the system a device for inhibiting such an erroneous access of the transmission frame.